This invention relates to semiconductor devices and more particularly to a static memory cell made of MOS transistors and an inverted field-effect transistor.
Static memory cells have the advantage of requiring no refresh overhead as needed in dynamic memories. Various static cell designs have been proposed such as that set forth in copending application Ser. No. 691,252, filed May 28, 1976, by G. R. Mohan Rao, now U.S. Pat. No. 4,246,692, assigned to Texas Instruments, which avoids refresh, but at the expense of larger cell size and increased power dissipation. Various "self-refreshing" cells have been used such as shown in U.S. Pat. No. 3,955,181, issued May 4, 1976 to Joseph H. Raymond, Jr., for Self-Refreshing Random Access Memory Cell, assigned to Texas Instruments. RAM cells of very simple construction are shown in pending U.S. patent application Ser. No. 700,989, filed June 29, 1976, by G. R. Mohan Rao, David J. McElroy and Gerald D. Rogers, now U.S. Pat. No. 4,070,653; Ser. No. 754,208, filed Dec. 27, 1976 by David J. McElroy, now U.S. Pat. No. 4,092,735, and Ser. No. 762,916, filed Jan. 27, 1977 by David J. McElroy, now U.S. Pat. No. 4,142,111, all assigned to Texas Instruments. These prior cells provide either static operation, or apparently static operation in that refresh is accomplished without addressing the cells, and are of successively smaller cell size and had operating or process advantages. However, continuing improvement in cell size or power dissipation, as well as process compatibility, became necessary with higher density memories of the 16 K and 64 K variety.
It is a principal object of this invention to provide improved memory cells in semiconductor integrated circuits. Another object is to provide an improved static cell for MOS memory devices, particularly a static cell of small size and low power dissipation. An additional object is to provide small area memory elements in semiconductor integrated circuits, particularly made by processes compatible with MOS-LSI standard products.